Verilog 学习笔记（8）：Multiplexers

2-to-1 multiplexer

Solution

module top_module( 
    input a, b, sel,
    output out ); 
assign out = sel ? b : a;
endmodule

2-to-1 bus multiplexer

Solution

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );

    assign out = sel ? b : a; //每一位允许自动匹配
endmodule

9-to-1 multiplexer

Solution

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );

  
    always @(*) begin 
        case (sel) 
            4'b0000:out = a;
            4'b0001:out = b;
            4'b0010:out = c;
            4'b0011:out = d;
            4'b0100:out = e;
            4'b0101:out = f;
            4'b0110:out = g;
            4'b0111:out = h;
            4'b1000:out = i;
            //default:out = 1;       //在输出端口16位宽的的时候不能直接写1
            default: out = 16'hFFFF; // 设置默认值为全1 （16进制）
        endcase
    end
            
endmodule

256-to-1 multiplexer

Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector using a variable index will work.

Solution

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );

    assign out = in[sel];
endmodule

256-to-1 4-bit multiplexer

Solution

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );

    assign out = {in[4*sel+3],in[4*sel+2],in[4*sel+1],in[4*sel]};
    //注意顺序应该是从高位到低位  
endmodule