其实在教程的每页都给出了详细的讲解,我将做些强调和补充。
Simple wire
特性 | assign 语句 | always 块 |
---|---|---|
赋值对象 | 只能赋值给 wire | 只能赋值给 reg |
触发方式 | 连续触发(右侧信号变化时) | 事件触发(如时钟边沿、电平变化) |
适用场景 | 组合逻辑(如门电路) | 时序逻辑(如寄存器)或复杂组合逻辑 |
赋值符号 | 使用 = | 时序逻辑用 <= ,组合逻辑用 = |
Solution
module top_module( input in, output out );
assign out = in;
endmodule
结合规则:
In a Verilog "continuous assignment" (assign left_side = right_side;
), the value of the signal on the right side is driven onto the wire on the left side.
Four wires
Solution
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
Inverter
module top_module( input in, output out );
assign out = ~in;
// ~ means NOT
endmodule
AND gate
这部分内容循循善诱,讲解细致。
If it sounds different, it's because I've started describing signals as being driven ( has a known value determined by something attached to it ) or not driven by something.
module top_module(
input a,
input b,
output out );
assign out = a & b;
// AND is '&', not '+'.
endmodule
NOR gate
module top_module(
input a,
input b,
output out );
assign out = ~(a | b);
endmodule
XNOR gate
异或非门,也称为同或门。
module top_module(
input a,
input b,
output out );
assign out = (a & b) | (~a & ~b);
endmodule
Declaring wires
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire and1;
assign and1 = a & b;
wire and2;
assign and2 = c & d;
assign out = and1 | and2;
assign out_n = ~out;
endmodule
7485 chip
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire p2cp2d;
assign p2cp2d = p2c & p2d;
wire p2ap2b;
assign p2ap2b = p2a & p2b;
assign p2y = p2cp2d | p2ap2b;
wire p1ap1cp1b;
assign p1ap1cp1b = p1a & p1c & p1b;
wire p1fp1ep1d;
assign p1fp1ep1d = p1f & p1e & p1d;
assign p1y = p1ap1cp1b | p1fp1ep1d;
endmodule